M48Z512A-70PM1

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Manufacturer Part

M48Z512A-70PM1

Manufacturer
STMicroelectronics
Description
IC NVSRAM 4MBIT PARALLEL 32PMDIP
Category
Integrated Circuits
Family
Memory
Series
-
InStock
2600
Datasheets Online
M48Z512A-70PM1 PDF
Inquiry
  • Series:-
  • Package:Tube
  • Part Status:Obsolete
  • Memory Type:Non-Volatile
  • Memory Format:NVSRAM
  • Technology:NVSRAM (Non-Volatile SRAM)
  • Memory Size:4Mb (512K x 8)
  • Memory Interface:Parallel
  • Clock Frequency:-
  • Write Cycle Time - Word, Page:70ns
  • Access Time:70 ns
  • Voltage - Supply:4.75V ~ 5.5V
  • Operating Temperature:0°C ~ 70°C (TA)
  • Mounting Type:Through Hole
  • Package / Case:32-DIP Module (0.600", 15.24mm)
  • Supplier Device Package:32-PMDIP Module
Shipping Delivery period For in-stock parts, orders are estimated to ship out in 3 days.
We ships orders once a day at about 5pm except Sunday.
Once shipped, estimated delivery time depends on the below couriers you chose.
DHL Express, 3-7 business days
DHL eCommerce,12-22 business days
FedEx International Priority, 3-7 business days
EMS, 10-15 business days
Registered Air Mail, 15-30 business days
Shipping rates Shipping rates for your order can be found in the shopping cart.
Shipping option We provide DHL, FedEx, UPS, EMS, SF Express, and Registered Air Mail international shipping.
Shipping tracking We will notify you by email with tracking number once order is shipped.
You can also find the tracking number in order history.
Returning / Warranty Returning Returns are normally accepted when completed within 30 days from date of shipment,please contact customer service for a return authorization.
Parts should be unused and in original packaging.
Customer has to take charge for the shipping.
Warranty All purchases come with a 30-day money-back return policy, plus a 90-day warranty against any manufacturing defects.
This warranty shall not apply to any item where defects have been caused by improper customer assembly, failure by customer to follow instructions, product modification, negligent or improper operation

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